On-die routers are typically designed with a pipelined architecture and the general trend is to reduce the pipeline depth for better performance. However, when power gating is applied to a router design, the performance typically suffers due to wake up delay when the power-gated functional blocks in the router are being activated. In these short-pipeline routers the performance impact from the wake up delay can be significant.
Typical on-die router designs assume a specific number of cycles of wake up delay and designers attempt to minimize the impact on performance by managing the power gating frequency and wake up/shut down strategies. However, these approaches have tradeoffs between power savings and performance decrease, preventing optimal operation.